Data converters for wireless standards by Chunlei Shi

By Chunlei Shi

This textual content offers the layout of knowledge converters for rising criteria and introduces the underlying circuit layout rules. it truly is an outstanding reference for IC and combined sign designers, layout managers and undertaking leaders in undefined, rather these within the instant semiconductor undefined.

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Figure 3-5 depicts the concept schematically. The effect of the finite reset time is to set an upper limit to the maximum phase-difference which can be detected PLL Building Blocks 37 before the PFD/CP output erroneously switches polarity. 10) with shows that which means that the phase-frequency detector must have a linear phase detection range that goes beyond ±180° at the highest operation frequency of interest. 3 Spectral Components of the Charge-Pump Output Signal Let us now calculate the spectral components of the output signal as a function of the phase error between and In the following analysis it is assumed that the output of the charge-pump consists of current pulses of amplitude and that there is no mismatch between the current sources of Figure 3-2.

75– 102, July 1913, Reprinted in Proceedings of the IEEE, Vol. 87, no. 11, Nov. 1999. [6] E. Armstrong, “The super-heterodyne - its origin, development, and some recent improvements,” Proceedings of the IRE, vol. 12, pp. 539–552, Oct. 1924. [7] B. Razavi, RF Microelectronics, Prentice Hall, New York, 1998. R. Thrower, “History of Tuning,” in International Conference on 100 Years of Radio, 1995, pp. 107–113. P. Robins, Phase Noise in Signal Sources, 9. , London, 2nd edition, 1996. B. Leeson, “A Simple Model of Feedback Oscillator Noise Spectrum,” Proceedings of the IEEE, vol.

From the point of view of noise performance, the double-balanced mixer and the sample-and-hold phase detector have the property that their output is 2 The pull-in range is the maximum difference between the VCO frequency and the “target” frequency that the loop can cope with, so that eventually frequency- and phase-lock is achieved. 32 Single-Loop Architectures active during a full reference period. This makes their design with respect to noise performance to be critical, and their noise contribution is likely to determine the PLL noise performance [6].

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